I know that there exist many disperse app note around how to export pin delay and why you should do that nevertheless I can’t find any comprehensive guide line which accompany you from A to Z of this process so I convinced to wrote down this post. For DDR3 and other sensitive high speed signals it is recommended to do the length matching with taking account package delay. This requirement only applied for non high-volume custom designed chips like Xilinx FPGA and other SoC’s available on market, in other word well-establish ICs like DDR chips pin delay’s had already been matched internally.
1. Open Vivado (my version is 2017.2)
2. On the TCL command window execute following commands
link_design -part xc7z020clg484-3 write_csv pin_delay.csv
Unfortunately output file of Vivado not work out of the box. You need to open the CSV file in some text editor (I use one of the most primitive one, Microsoft Excel) and remove the trivia rows and columns from it. Next thing is that Vivado export package delay in terms of
Max Delay and
Min Delay but Allegro only support Pin Delay. So you have to choose between the two or doing some math and get an average.
1. Remove all rows until only pins or banks remain without any empty row or heading
2. Remove all columns except Pin Name (like A9) and one of
Max Delay or
3. Add Unit. Vivado output delay in ps unit but allegro may not compromise with this choice. To overcome this issue, you need to add
ps to the end of all delay values. In Microsoft Excel in a new column (we assume C is new column and delay values are in column B) write formula
4. get gripper from bottom corner of cell and drag it all the way down
5. copy column C and press
V to paste special into B column. (I hate Excel, use bash+sed)
6. save file into a CSV file and open Allegro
1. Go to
File > Import > Pin Delay, select CSV file and click on your chip.
2. Pick Import button and close the Pin Delay form.
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